1. Field of the Invention
The present invention relates to a data processor such as a microprocessor which is provided with pipelining system for processing instructions and capable of accessing operand of instruction under stack-push addressing mode and stack-pop addressing mode.
2. Description of the Prior Art
FIG. 1 is the schematic diagram of pipelining system of a conventional data processor.
Referring to FIG. 1, the reference numeral 1 denotes an address calculation stage, 2 an execution stage, and 3 a stackpointer, respectively.
FIG. 2 is the schematic diagram explaining operations of the pipelining system shown in FIG. 1. FIG. 2 (a) denotes instructions and 2 (b) a pipelining process when executing those instructions shown in FIG. 2 (a).
Conventionally, when executing instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, it is assumed that the stackpointer 3 is renewed simultaneously with the calculation of the operand address. However, when executing those instructions mentioned above by applying pipelining process, even if a new stackpointer value is calculated at the address calculation stage 1, the preceding instruction being executed at the execution stage 2 may refer to the past stackpointer value. To prevent this, the present instruction is obliged to stand by itself at the address calculation stage 1 until the preceding instruction passes through the execution stage 2.
For example, operations of the conventional pipelining system when consecutively executing two instructions including the designation of operands under stack-push addressing mode ("PUSH" shown in FIG. 2 (a)) is described below.
Assume that the stackpointer value before executing an instruction I1 is SP, first, at the address calculation stage 1, an operand address of the instruction I1 is calculated, and as a result, the address "SP-4" is outputted. Nevertheless, since another instruction preceding the instruction I1 may access the stackpointer 3 at the same time, actually, the value of the stackpointer 3 cannot be renewed. Actually, this value can be renewed simultaneously with the executing of the instruction I1 at the execution stage 2. Furthermore, since the operand address of an instruction I2 following instruction I1 cannot be calculated before the new stackpointer value "SP-4" generated by the instruction I1 is actually written into the stackpointer, calculation of the operand address of the instruction I2 is executed after renewing the content of the stackpointer 3.
As mentioned above, in conjunction with the pipelining process executed by any conventional data processor, when executing a plurality of instructions including the designation of operands under stack-push addressing mode and stack-pop addressing mode, actually, only one of those instructions can be operated, and as a result, any conventional data processor still cannot achieve the eventual object of pipelining process for improving the throughput by executing a number of instructions in parallel using a plurality of function stakes.